# OcuLink Expansion Bay Module

**URL:** <https://community.frame.work/t/oculink-expansion-bay-module/31898>\
**Category:** Expansion Bay\
**Created:** [June 5, 2023, 12:40am UTC](https://community.frame.work/t/oculink-expansion-bay-module/31898 "2023-06-05T00:40:26Z")\
**Posts on this page:** 1\
**Showing post:** 854

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**Author:** ![Filip](https://avatars.discourse-cdn.com/v4/letter/f/919ad9/32.png) [@Filip](https://community.frame.work/u/Filip)\
**Post date:** [November 15, 2025, 12:43pm UTC](https://community.frame.work/t/oculink-expansion-bay-module/31898/854 "2025-11-15T12:43:18Z")

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I used `JLC04161H-3313`stackup from JLCPCB and used their calculator to get the diff pair trace width and spacing.

But like I said, I doubt its my routing causing the issue since PCIe 1.0 should be able to work. I feel like I’m just missing something, although I do not know what it could be.

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