Hi, I bought the expansion bay module form your link (i2clabs.com.au), I tried contacting you via email and phone to get a few information, could you please contact me back?
My email probably got into spam, thank you in advance.
josh hasn’t replied to anyone in half a year. If you’re still in the time window, I’d try to get the money back via PayPal or your credit card or whatever you used to pay.
Yup, do exactly that. I’m outside the window, so I’m basically out of luck since Josh disappeared. Tried emailing him multiple times and tried doing a chargeback but I’m sadly out of window. It’s not safe to buy anything from Josh at this point and I don’t see myself trusting him anymore due to taking money and disappearing.
I have looked into reporting his Stripe URLs to Stripe for fraud (so they take them down in order for more people to not give him any money), but I could not find any email or form for it.
Thanks, will do.
Since this option is not available anymore are there other ways to get oculink 8i on the FW16?
I read a big portion of this thread and I have not yet reached a conclusion, am I missing something?
Gu_tally has a prototype which seems to be working with some workarounds, but he’s busy with his dissertation right now and will hopefully continue on the project in one or two months.
You can also take a look at this OcuLink eGPU works with the Dual M.2 expansion bay module - #136 by Echelon
Which is a 4i Oculink via the SSD expansion bay and M2 to Oculink adapters. It’s a bit more funky, but at least available right now.
I have seen the M2 one and I had a doubt, I am not an expert on the PCIe bus and a question came to my mind, since it seems that the PCIe x8 made available by the interposer can be used in its entirety (with the first party RX 7700M) or split in 2 for the M2 expansion bay module would it be theoretically possible to us a oculink 4i adapter on both the M2 slots, a 2x4i to 8i cable and a 8i dock?
In other words, is the PCIe splitting feature implemented at the hardware level in the M2 expansion bay module or obtained with some kind of autodetection by the BIOS making it possible to have 8 lanes by using both the M2 slots?
no it will not. you cannot merge two 4i to an 8i without a very expansive PLX chip.
The splitting happens via what the embedded controller gets from the EEPROM on the expansion bay board, so it should technically be possible to modify the EEPROM or slightly modify the EC firmware to force it to use 1x8 instead of 2x4 splitting.
Yeah could change the eeprom for beeing detected as an dGPU by the ec. So it is usable as 8i.
For the Laptop itself its irelevant if its an dgpu or an 8i egpu and handles it the same. But in the current buggy ec state. No ine knows how hard the impact on powermanagement etc is.
Is it tecnically possible?
If I were to extract the data from the EEPROM chip would you (or anyone on this thread) be able to help me decipher it and, hopefully, test this theory out?
I have already looked at the embedded controller code and should be able to modify it through there. And the format that the EEPROM stores this data isn’t that hard to figure out since it is also defined in that code. I would just need to get myself the M.2 card and the adapters necessary for 8i oculink to actually test this theory out. I will probably do it in a few weeks, just a bit short on funds right now.
No need to reverse engineer anything, Framework has a generator tool for the contents of the eeprom:
Do any of the designs proposed here make use of a retimer/redriver?
I know they can be quite costly but they would most definitely resolve the issues in getting gen4 working, I was thinking of something like a PI3EQX16908GL to keep cost relatively low.
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The problem is not with convincing the module to report as 1x8 instead of 2x4. The problem is with data integrity. With 2 devices of x4, it doesn’t matter for both of them to be perfectly in sync, as the CPU talks to them independently. But for a single x8 device, it is crucial for all PCIe lanes to be in sync.
Given that, neither the 2x M.2 module, nor 8i to 2x4i cables are engineered to match the length of paths/cables between 2 devices, only inside a single device. Without them being length matched all the way it is just a gamble if it will work for you or not. It may also appear to work but be very unstable. PLX chip would take care of it, if the timing is close enough for it to fix it, but that is expensive and still a gamble.
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I started to design a dual 4x oculink PCB, with the goal of it being connected to one singular 1x8 link. I have everything I need to do now to do it, I just need to do the routing. I understand the problems w data integrity but I think its 100% doable. I may also just use a singular 8i link instead of two 4i links. I got a test PCB from framework and I do intend to have DP in!
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Is there any reason why you (and Gu_tally) are opting for 2x 4i instead of 1x8. Two connectors just means its more likely something breaks on the connector side, right? Is there some advantage you get from going for 2x4i?
@Gu_tally just a community request, once you have the time to continue working on the board, it would be really amazing if you could try to make the next iteration just a bit smaller so it does not stick out of the back, even a couple of millimeters. Like this someone else could create a flat 3D print cover and we could have a really seamless solution. Thanks a lot!
It’s 2025 and I still believe in what I said lol
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the reason for a two 4i is because I only have a 2 4i to 1 8i cable that works withmy existing PCIe board… I do have a oculink 8i to 8i cable but it has series signal issue when connected… the 2 4i proves to be more stable with the current setup
for now…
still the progress resumes and new version(still a 2x4i) with modified layout and a EEPROM will be made soon™
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