You might be confused what “physical address space” is.
Physical memory is the actual RAM. Where the addresses are basically contiguous.
In a system where you have virtual memory, which you will have if you have significant dynamic allocations and don’t want your memory to fragment, the addresses that are used by 99% of software are virtual addresses.
Hardware translates these on accesses to physical addresses. So that you can have contiguous virtual memory ranges for the software mapped to non-contiguous physical memory, which you can swap out or move around without affecting the virtual addresses.
In such a system, a virtual address is resolved to almost any physical memory address. The lookup tables used need to fit any physical address. Because otherwise you could not dynamically allocate the memory in any order.
What you describe as “mapping”, is the OS / driver adding an entry into the respective page table, that associates a free, physical block of memory with a newly allocated virtual block of memory.
But the page table and address translation hardware was already designed to fit any physical memory address and the page tables are already designed to scale. And typically you have more virtual addresses than physical, so you can actually underprovision the memory, so you wouldn’t typically run out of virtual memory address space, before running out of physical one.
Limiting the bitwidths of physical addresses that can be resolved would run counter to everything. That would lead to a system, with supposedly shared memory, where you can access 100% from the CPU, but only the first 25% from the iGPU? This can only work, if the OS will try its very best to never use the first 25% for CPU-uses. Because once those are used, you starve the GPU of any memory. That would lead to static allocation in practice, having to reserve the memory. So no, that is not how that is done.
Also, don’t forget, that we are talking about multiple components, sharing a Die on the same technology node and the core interconnect and memory controller. Why would you want to save a few bits on one of the components attached to such an interconnect, when all the other components can make that work on the same technology node? Its the same interconnect, handling all of it. You would strive to reuse the same building blocks for the address translation in all the places.