The company announced their 3rd generation RISC-V mainboard. As I couldn’t find this topic, I created this thread. Feel free to discuss. 
News release:
Product page:
Media articles:
3 Likes
Cool! It’s very nice how fast DC Computing iterates.
Feels like a lot of the RISC-V landscape is moving at a pace far faster than x86
Specsheet TL;DR:
Main SoC: SpacemiT K3, 8-core CPU, up to 2.5GHz (Supports RV23 Vector set!!)
AI Acceleration: 30 TOPS NPU
Memory: 16GB / 32GB LPDDR5 (dual-chip)
2 Likes
For more information about the chip (including the GPU), a overview can be found here (note this is the variant with 2 core clusters, DC seems to be using 1):
Another TL;DR:
X100 Cores (CPU) have SPECint2006 ~9/GHz (it runs at 2.5GHz). This isn’t all that amazing, other RISC-V processors (e.g. XiangShan have ~15/GHz of SPECint2006, SiFive P800 ~18/GHz but that’s also not common anywhere for purchase)
For comparison, the cores in the DC ROMA II had an advertised score of 8.65/GHz. That did however run at 2.0 GHz, thus maybe a ~30% speed increase is expected. It seems the main selling point of this generation is the RVV support (which is indeed very exciting).
A100 Cores (AI accelerator) advertise support for 1024-bit RVV extension, and run at theoretically 30 TOPS (I would assume INT4?).
One last reply for this chain;
If you’d like a more general idea of where this chip slots in, here is a graph (SpecINT 2006 / GHz). Once again, advertised score of core in ROMA III is 9/GHz.
1 Like
Sorry to add another message to the chain,
@yuning_liang I am wondering what is barrier to using SODIMM memory connector instead of soldered memory. Especially this memory market this seem maybe more economical to allow people bring their own memory.
Is it issue with the DDR PHY on the SOC?
This is an amazing step up from the mainboard II board.
One thing that would be really good would be usb 4 / thunderbolt 3 support, because then all the usb devices that work with the FW13 mainboard would also work with this one.
With just usb 3.2, it is more similar to the FW12, usb wise.
1 Like
The NPU in this case really seems to just be another cluster of CPU cores (which are heavily optimized for INT Vector instructions). This seems much easier to program compared to the typical NPU which is nice.
Amazing to see! Why does DeepComputing use soldered ram for the boards by the way? Is there any specific reason? I’ve heard something about ARM boards usually being soldered as well on computers
1 Like