A few remarks/confirmations/additions:
USB4 has 20/40GBit/s before encoding, while TB3 actually had 20/40GBit/s after encoding, so actually ran at 41.25 GBit/s (called TB3 legacy speeds in USB4 spec). Whether USB4 makes this up somewhere in the protocol and whether TB4 will only use USB4 speeds I do not know. In practice it is hard to come close to that bandwidth, so it has not mattered so far.
Correct. In TB3 (also TB4 Hub in TB3 mode) the dock will have a PCIe/USB Controller (For USB3 and USB2). In USB4/TB4 with TB4 docks, this just looks like a USB-Hub to the host. The Host TB4 controller is the PCIe/USB3 controller, (at least with maple ridge) the regular USB2 controller of the system is used and USB2 just routed through the TB4 controller. Probably something to do with the wake-from-sleep-by-input features, standby power saving and early-boot input.
Somewhat. 1st gen / Alpine Ridge Controllers only supported HBR2, but 2x 4xHBR2 was possible. Titan Ridge added support for HBR3, but TB does not have enough bandwidth for 2 full 4xHBR3 connections. Same holds for USB4. More on that below.
Whether it is a TB4 certification requirement to support 2 HBR3 links I do not know. The Intel provided table of minimum monitor support (2x4K60 or 1x8K60) could be satisfied by 4xHBR2 link + 4xHBR3 link, which still does not fit through the same TB link. Although I have not seen such asymmetric configs from Intel systems, only AMD desktop systems which may not have certification. I would translate the spec into:
- must support 2 distinct DP links, each at minimum 4xHBR2
- must support at least 1 DP link with HBR3 speeds AND DSC to achieve 8K60
Correct. So far, the host TB-controllers only had at most 2 DP links available. But you can access these 2 links at any point of a TB3 / TB4 hierarchy. I.E. one TB dock uses 1 DP. TB-Out daisy chained to a second dock that can access the other DP link. Or even access one of those DP links via a second TB hierarchy also attached to the same host controller. In that case one is no longer limited by TB bandwidth and can access 2 full HBR3 links, if the host has that available.
I do not know whether it is a protocol limitation of USB4 to only support 2 DP links at most. It may just be an Intel limitation as so far, all Intel TB controllers, even those inside Tiger Lake (2 controllers for 2 TB-ports each) only have 2 DP links available, which they may distribute across the 2 possible TB-Ports.
So for Framework, 2 of the USB4 ports will internally share a controller and therefore share 2 DP links between them. As other 4-TB port notebooks with Tiger Lake have one controller for each side, this is probably also the case for Framework.
Bandwidth allocation for tunneling DP though TB:
As far as I know and tested, DP links through TB have their bandwidth statically allocated on a first-come-first-serve basis. As DP SST displays only use the connection speed required for the desired resolution, if you connect a 4K60 display, only a 4xHBR2 link will be established, with the max 4xHBR2 data rate of ~17.3 GBit/s allocated to that link.
A second display can then still establish a second 4xHBR2 connection, as there is enough bandwidth left. If the first connection that gets established uses 4xHBR3 however ~25.9 GBit/s get allocated. If not enough unallocated bandwidth is available, the DP links will be downgraded, similar to when using lesser cables. In practice I have seen 4xHBR3 + 4xHBR1 and 4xHBR3 + 2xHBR2. Dell lists their docks as using 4xHBR3 + 1xHBR3. I have no idea, whether Displayport devices are smart and flexible enough to find the exact configuration that still can supply the most bandwidth (i.e. 2xHBR2 provides more bandwidth than 1xHBR3), or whether they will just downgrade the speed at whatever amount of lanes they want (USB-C monitors are so far, statically configured inside the OSD whether to seek 2xDP+2xUSB or 4xDP Alt Mode)
This concept of the maximum data rate of the link being allocated to it also worked in 20Gbit/s TB4 mode, where either only 1 4xHBR2 link or for example 2 4xHBR1 link could be established.
If a monitor is driven with less than its native resolution (not upscaled by GPU) the Displayport link may also get downgraded and require less bandwidth of Thunderbolt.
However in my experience MST-Hubs, like those in DP daisy-chainable displays or the popular Dell, Lenovo, HP docks will always establish the highest link speed supported, so they do not have to renegotiate when new displays are attached. But they seem to also only establish their connection, when at least a single sink/monitor is attached, so DP bandwidth allocation can be controlled by connecting displays one after the other in the desired order.
If however a TB Hub / Dock with multiple displays already attached is connected to the host, the internal display outputs of each TB-controller seem to have a static priority, that is used to decide the order in which DP connections are established and get their bandwidth allocated.
Within each DP link speed, the actually used DP bandwidth does not matter for the above described allocation process. But if there is bandwidth left over, like when driving a single FHD60 display behind a TB3 dock with built-in HBR3 MST Hub (4xHBR3 / ~25.9 GBit/s allocated for this link, but only ~3.4 GBit/s actually used) the difference in bandwidth can still be used by other data than Displayport, like USB and PCIe traffic.
But it seems, at least so far, that TB will never thin-provision Displayport links depending on what amount of bandwidth is currently taken up by displays (even though Intel describes in one of their whitepapers that TB controllers sniff that number out of the DP links, to correctly prioritize DP communication above all else).