ECC support?

[Xavier_Jiang]

Continuing the discussion from @Adrian_Joachim, @John and .. nobody else.

@Adrian_Joachim

either lpddr or ecc but not both at the same time.

LPDDR is never ECC, lol. Though, you can get DDR low-power to do ECC. I have some DDR3L-Reg ECC. Which is different than LPDDR3.

Any host that take DDR3 can take DDR3L, its just lower voltages.
Havent seen DDR3L-non-reg ECC.

The reason is likely bus width. ECC use 72-bit bus width (64 + 8), you can’t do that with LP dies.
On ECC ram you physically have more chips. 1 extra, to be exact. For the 8 bit parity data. Though it also can manifest as 5-chip modules, if some of the chips have multiple dies in them. But always multiples of 3 or 5.

If you get a module with even number of chips claiming ECC, you get scammed. Only exception is registered RAM, which have a extra large chip as the register. So, ECC Reg would be 10 chips. Or 6, etc.

ECC would be real nice. Though seem like it is now possible.

[Obasav]

Take what the AMD website says with a grain of salt. They said it was possible with 78/7940HS, and then changed it after enough people found out they locked it to pro series cpus…

[Xavier_Jiang]

@Obasav

pro

Supposedly 7840HS is a pro, but apparently not?

Seems like it was, but they later on scrapped it. Not sure how/why. If you look on their website, no 7840HS “pro” exist, and 7840HS says no ECC support.

AMD has always been locking ECC to Pro CPUs, if said CPU have a iGPU. Not entirely sure why, since the non-pro support 72-bit widths. But not ECC code. Might be so that they can fuse off some memory controller modules to improve yield.

[Adrian_Joachim]

@Xavier_Jiang

LPDDR is never ECC

This is false on multiple levels, first of all lpddr has internal ecc and at least nvidia is using lpddr with end to end ecc on their arm servers. End to end ecc has little to do with the actual memory chips and more with how the memory controller uses them.

If you look at a stick of ddr memory it doesn’t use different ram chips than non ecc, it just uses more of them.

@Xavier_Jiang

I have some DDR3L-Reg ECC. Which is different than LPDDR3.

DDR3 is also ddr3, a lot has happened since then.

I don’t know if amd supports ecc with lpddr (probably not) but there is nothing stopping them from using an extra ram chip with lpddr just as they would with regular ddr, the actual ecc bit is in the memory controller.

@Xavier_Jiang

Not entirely sure why, since the non-pro support 72-bit widths. But not ECC code. Might be so that they can fuse off some memory controller modules to improve yield.

I would bet it is purely market segmentation and probably not even fused off just disabled in firmware/microcode.

[LiKenun]

I have a HP Z2 Mini G1a workstation with link ECC. It’s the only Ryzen-based computer I’ve encountered that supports any form of ECC. The tear-down of the workstation shows it does not have extra DRAM chips for the parity bits though, so it’s not a full-fat ECC implementation, but it does fulfill the important requirement that the transmission of the bits between the RAM and CPU are protected.

[Jorg_Mertin]

When I built my last server, home and low power, I came up to use a ryzen embedded which supports ecc.

Server build blog

Amazing piece of hardware. Really nice. Wonder why they don’t use these CPU’s in laptops.

[Xavier_Jiang]

@Jorg_Mertin

ryzen embedded

They are so obscenely expensive. A board with that chip goes for like $1,500 minimum (new), and they aren’t even that fast.

Low key with a 54W power budget, you can almost put a LGA 115X/1200 chip in here. Or full AM4/AM5 chip. Those come with ecc (Xeon e3/E or EPYC 4004). Minus the massive size, of course.

But to get back. It’s also embedded sector, not mobile sector. Power saving (variable core frequency, etc) is sometimes not a concern, oddly.

Which is also why your board doesn’t take ATX-24. It’s intended to be fed 12-24V DC from a external source. Or a internal 1-rail power supply part of chassis.

ATX PSU bits

You said you jumped “Power Good”. That is un-true, you jumped PS_ON. Power Good goes to 5 V when power supply is able to supply nominal voltages, so the main board can turn on.

A computer without PG will simply not POST. It will power on, all fans and such, but hang at 0xFF until PG is asserted (pulled high), then post.

Its only for the real picky people that want ECC on the edge, but is too power constrained to want a consumer socket xeon/epyc (which didnt exist for AMD back then).

See Xeon-D for embedded. For mobile, see Xeon-M, or Xeon E-M..

For like a total of 3 machines in the last 5 years, you can get mobile xeons with ECC. Thinkpad P71, P17 Gen 2, Dell Precision 7720/7540/7560, 5540, HP ZBook Fury 17 G8.
oK 4, maybe 8 if you include refreshes. You can count on one hand.

[Jorg_Mertin]

@Xavier_Jiang

They are so obscenely expensive. A board with that chip goes for like $1,500 minimum (new), and they aren’t even that fast.

Maybe, but since I actually use ECC on my server, I never had an issue or unknown reboot cause (which I had with all other servers architecture I had in the past).
In the end, even though they are expensive, I spent way less time trying to troubleshoot the reboot/crash cause. And that lost time, money can’t buy!

[Xavier_Jiang]

@Adrian_Joachim

end to end ecc

LPDDR5X have end to end. LPDDR5 don’t.
at least micron blog talks about it.
I am trying to find any info on this, but can’t.

So the “on die ecc” is probably the in-line ecc, which is cool, but dont check for end-to-end.

@Adrian_Joachim

nvidia

Well, if you have a custom chip with .. what, a 512 bit wide memory bus, you can probably figure out some ECC with 32-bit packages.

Though seems like Nvidia is using the inline version, not the sideband version. I could be wrong, and I hope they have some sideband ecc going on.

Their two 8-chip-per-side rendering of their grace CPUs does not inspire confidence.

in theory they are mostly the same, if you request 8x64 bit of info and then get 1x64 bit of parity, so long as the line doesnt fault twice on any single bit, you can correct.

This is a bit different than 8x(64+8) bit. In this case, you can outright lose 8-bit, they can fault 100% the time, and you can still reconstruct data.