Hi, this is a very long thread so forgive that I’ve not read all of it. Does this mean that currently there are no solutions with DP in, so an eGPU always requires an external display?
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Yes and no.
No DP in so far, that definitely requires a custom PCB, and we don’t have that.
But you can still use the internal screen, it will just have to send it back through the PCIe (which is already limited), to the iGPU, which will display it on the internal screen. It sounds bad, and it kinda is, but it’s definitely useable.
It’s still easily possible to use it for competitive gaming even at full monitor res.
And if you record your gameplay anyway, something very similar would be happening even with DP in - if you’d use the iGPU for encoding (e.g. if your eGPU is older and has no AV1 HW encoder) you would still be sending the frames to the iGPU just the same. But even if you use the dGPU for encoding, it would need to send the compressed frames through the PCIe link to the CPU. Much less, admittedly, still, very similar.
So don’t worry about this too much. Yes, you’ll loose a few percent, still, it’s a very viable solution.
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Just adding some random info from my setup. I’ve got my Oculink port wired into the M.2 just like a lot of you, but I got my hands on a MCIO x8 → 2x Oculink (4x) cable, so I picked up a 2xMCIOx8 to PCIe adapter board, now if I had all the MCIO lanes I could get this running at x16, but I’ve just got the 1 Oculink port coming out of the Framework (for now). I’ve got a successful PCIe gen 3 link to my 1050Ti (best card I have at the moment I can use).
So my current chain is : Framework → dual M.2 board → M.2→OCuLink (x4) → cable (MCIOx8 to 2x Oculink x4) → MCIO→PCIe adapter → PCIe×16 slot → 1050Ti
Once I’ve got a bit more I can put into the experiment I want to pick up a second M.2 to Oculink cable and see if I can’t get x8 working some how. I don’t expect it to work, but shrug what’s there to loose trying.
I’m still very much hoping someone comes up with an official Oculink board, (or for that matter at this point MCIO might be the better connector if we want x8 out of the system) that we can use to hook up external devices without cobbling together a solution.
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As far as I know, others have tried this with the NVME expansion bay, but it is not possible. The firmware of the board tells the CPU to split the 8 lanes into 2x4, which means you cannot use them as a single connector.
it looks like that soon it will be possible to reprogram eeprom EXAMPLES: Document flashing eeprom · FrameworkComputer/framework-system@85c4b2f · GitHub
The eeprom on the nvme bay is read by the EC and then the BIOS acts on it. It would not be difficult to add an ectool command to the EC firmware to override the 4x vs 8x lane setting.
It would probably be easier than reprogramming the eeprom.
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The problem there is that the traces are likely not routed to the same length for both slots.
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The length difference between different pairs (inter-pair skew) does not matter that much to the spec from the various PCIe routing guides I’ve read. What’s important is the length of the two traces of a pair (intra-pair skew) and that needs to be at max 5 mils and the m.2 card definitely has that as otherwise it wouldn’t work by itself. So its definitely doable.
I wonder why pci cards go through the trouble to match them then.
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It makes it easier to route if you keep them all together, you’re routing them all to the same place anyways.
Can confirm its possible to reflash the EEPROM as long as the write protect pin on it is not set to high, which hopefully it isn’t. I’ve made my custom board for testing things on the expansion bay and just used ectool to reflash the EEPROM without issues. Only thing is that if you mess it up, it could result in the laptop itself not booting which is what happened to me, so I needed to flash the EEPROM using a separate flashing board outside of the laptop. (although, if some GPIO pins are configured differently to what the board expects, I assume it can also break something)
You basically just reflash and reboot the laptop and it should load up the config.
Some cards I saw wiggle the traces on the inner radii of bends so that they match in length to the lengths of traces on the outer radii.
That’s definitely an extra effort made to keep the intra-pair skew low
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The recommended trace length difference between different pairs is several inches (think 7 for “system boards” and 2 for “add-in” cards) for gen 4 (at least according to some document I found), so for most cases it will be negligible. Even if you were to go above that recommendation it would most likely be fine, but I doubt you have such a huge difference even with the M.2 card. But yes, you can easily do those wiggles to make all the traces have the same length.
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I just found the specs for gen 4.0 and it lists 5ns as maximum allowed inter-pair skew. Even if the signal were to travel at 50% of speed of light you would still get over half a meter for 5ns.
I guess this is why the TI document I read just says “There is no need to match inter-pair skew.”
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@Filip is correct.
As part of the PCIe link training, while it needs a TX pair to be equal length, it can handle quite I high length variance between different TX pairs.
Unfortunately, the registers that store the measured link differences so it can correct them are not normally made available for software to read them.
What is of far more concern is the quality of the cable links. Immunity to noise, impedance matched and short enough length. Traces across the surface of a PCB are not shielded from RF interference and other noise sources.
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Apparently someone in the other thread has designed one. and someone else is testing the m.2 board to oculink4 without cable. OcuLink eGPU works with the Dual M.2 expansion bay module - #312 by OVER_CL0CK
Would like to clarify as I am the one currently testing it, I am still using an oculink cable. Specifically for the DEG1. Unless you are referring to the ribbon inside the expansion bay that everyone has been having issues with fitment for as the “cable”, then that would be correct. This is a straight m.2 card, makes fitment much easier.
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I have been playing around with my own oculink 8i board that I got produced, but it seems like I am getting no life from the laptop to initialize the GPU. I have double checked my diff pair wiring with the m.2 expansion bay board through a 4i oculink adapter, so the pairs and refclk are definitely connected correctly.
The only issue I can imagine is if my CLKREQ or PERST wiring isn’t right. I did try to connect CLKREQ directly to GND and then also 3.3V through a 10kOhm resistor, as according to this PCIe For Hackers: Link Anatomy | Hackaday article, CLKREQ should be pulled down to request the clock signal. For PERST I connected it directly to the oculink port but I did also try to do the same things I did with CLKREQ to no avail. The laptop simply does nothing to try to initialize the link to the GPU even after that. By “initialize” I mean that the GPU doesn’t show up at all, no enumeration, nothing.
I would greatly appreciate if someone with more know-how could help with this, as I am completely stuck with the project and have no way to proceed. I unfortunately also have no oscilloscope to test if I am actually receiving any signal. @Gu_tally do you perhaps have any basic schematic to show how the wiring is connected? I’ll be editing this post shortly to post my KiCad project if anyone wants to check out what I could have done wrong.
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Just to double check, does your board have a eeprom chip to tell EC that it’s a GPU card? 
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Yes, it indeed does and framework_tool --expansion-bay does indeed return that everything is okay and PCIe is set to 1x8. I did finally get around to writing some docs on the repository so here it is if someone wants to check it out GitHub - Terrails/FW16-OCuLink . The first revision of the board I made and got produced didnt have any trace connected to CLKREQ pin so I did have to add a really tiny wire there to connect it to GND, but the revision in the repo includes that now.
EDIT: I did not mention this in the docs, but I did connect REFCLK and PERST to both A and B “side” of the oculink connector (I assume this is for when you use a 2x 4i to single 8i cable). I just have a simple 0R resistor there acting as a jumper to disconnect. It was really hard to find some kind of x8 oculink pinout, so I just decided to play it safe and have both sides connected, but it didn’t make a difference to getting any enumeration.
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