According to intel product page, core-ultra-155h has PCIe-5.0 support (8 lanes). How does Framework’s motherboard use these PCIe-5.0 lanes? I’m particularly interested if maybe M.2-PCIe slot (NVMe) uses these 5.0 lanes, so that I could fully utilize PCIe-5.0 NVMe SSD speeds? I was trying to find this info in specs, but no luck… Also, I’m aware that currently most PCIe-5.0 NVMe SSDs require huge radiators, but I’m asking with future upgrades in mind when heat production of future models hopefully decreases to reasonable levels.
I believe currently the Core Ultra Series still uses PCIe 4.0 for the NVMe slot. If it were using PCIe 5, there would likely be an update from Framework or the capability would be listed in the specs.
What Intel’s product page doesn’t mention is that the CPU is actually 4 separate chips (which Intel calls tiles) working together. One of those chips is the SOC tile, which is essentially a mini CPU that is fully active while the other chips only activate when needed to supplement the SOC tile.
The PCIe 4.0 lanes are directly from the SOC tile, however the PCIe 5.0 lanes are from the IO tile (which handles PCIe 5.0 and Thunderbolt).
That means that using the PCIe 5.0 lanes (even if it is only with a PCIe 4.0 or 3.0 device) will result in short battery life due to forcing the IO tile to stay on more and due to creating a need for communication between the tiles (which also consumes power).
Afaik most Core Ultra laptops that actually use the PCIe 5.0 lanes usually use those lanes for a dGPU because when a dGPU is active users usually don’t care much about battery life and only care about performance.
Afaik on the Framework Laptop 13 everything uses the PCIe 4.0 lanes from the SOC tile and the PCIe 5.0 lanes from the IO tile are unused.
Yep. Mainboard schematic is also up now, confirming this.
And while PCIe ports are generally universal, even if they would not be on separate tiles, it’d be very likely that most manufacturers stick to connecting the standard components as Intel specs it, just because that will be the best tested variant. And there might be a bunch of other optimizations not easily visible for power efficiency etc.
Also, schematics confirm Hayden Bridge ReTimers. Nice to see that on official documents. Since with 13th gen we had to guess that Framework bottlenecked the hardware with the old ReTimers.
I’d imagine there are more detailed guidelines under NDA for manufacturers what to do and configure for best results or what recommended options would be. So we cannot be sure. But the port does not support bifurcation at all (its designed to be x8-wide, it will be under-utilized with x4. Which could add to inefficiency). But clearly, it was not a focus to design this as a recommended way to connect the SSD. Then it would be bifurcatable into x4+x4.
But I think its a good bet that these kinds of diagrams reflect what Intel has as reference designs and would therefore be the easiest to implement with everybody having the most experience with already etc.
Like FW said regarding their time-to-market for new products: they do not want to be first with any brand new component or feature, where they’d have to find bugs for which they’d then have to ask suppliers to develop fixes for so they can progress.
So the first 2 x4 Gen 4 ports directly from the SoC Tile are the bifurcatable ones that would be used for WiFi and other small stuff (what was previously chipset lanes). Only the 3rd SoC Tile port is strictly x4 and probably the primary port meant for SSDs. The other 2 x4 Ports listed in the overview graphic as for SSDs are from the IO Tile.
Although, of course, if not all smaller ports are needed, you may be able to use one of them for a 2nd SSD directly on the SoC Tile.
Many thanks