I have been working on my own Expansion Bay board and was wondering what exactly the TX and RX lines are. I have initially connected the TX lines directly to receive pins and RX directly to transmit pins of my PCIe device. The issue is that the first run of the board is not responding.
I did some troubleshooting and the pinout seems right, so it seems like I have had a wrong understanding of the TX and RX pins. After taking another look at the README on the Repo, I noticed that TX lines are marked as I (Input) and RX lines as O (Output).
Am I right in assuming that the TX lines from the interposer should then connect to the TX of the device (so the device transmits its data to the mainboard TX since its marked as input) and then the opposite for RX?
I would love a confirmation if this would then be right. Don’t really want to order a 2nd batch and for it to not work again lol.
Looking at the schematics.
There is this type of symbol:
That above one means the signal is going in the left to right direction.
So, for example, the one labeled: PEG_CRX_GTX_P2 is going from the GPU connector towards the CPU.
Does that help.
Caveat: That is assuming the schematic is correct. The schematic seems to mix symbols around a bit, so it might still be wrong.
From the README link above.
The “VSYS_GPU” is marked with an “I” and has description: “Main power rail to Expansion Bay Modules from Vsys”.
So, I would say “I” is in the direction from the CPU to the Expansion bay.
and “O” would be in the direction from the Expansion bay to the CPU.
Is that the way you have them connected up?
Caveat, I have not built a PCB for the FW16, so I might be wrong.
I was connecting TX (so the pins marked as “I”) to the RX pins of the device and RX (marked as “O”) to the TX pins. I initially thought the pin names were from the direction of the mainboard, so TX would send out data to the RX on the other side and RX would receive data from TX on the other side.
I have now taken a look at the M.2 example board and the RX pins from the interposer are connected to the RX on the M.2 slots and TX to TX, so it looks like my initial boards were completely wrong and I have to swap the pins.
I’ve got a slightly different question. I know that polarity reversal is a required part of the PCIe spec, so I assume that indeed works as it will make routing easier.
But if anyone from Framework could answer, is there support for the optional lane reversal feature of PCIe? This would help me with mitigating the number of vias on my board, so it would be great if information on this could be known.
