PCIe lanes per port (Intel) and usb xDCI

I am about to pull the trigger on the 13" Intel laptop but before I do I have a few questions.

  1. Is it true that all four modules are TB4? For example with 4x TB passthrough modules, can I plug in 4x Thunderbolt devices and use them concurrently?

  2. If so, how many PCIe lanes does each port have allocated? Is it a 4 per port, ie 16 total lanes?

  3. As the raptor lake platform supports an xDCI interface natively (General Capabilities - 005 - ID:743844 | 13th Generation Intel® Core™ Processors) does the uEFI configuration support enabling it? If not, can that be enabled in the uEFI configs (advanced chipset menú or similar)?

Thanks in advance. This platform looks super amazing!

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  1. Yes, but there are only two controllers on each side, so you would share bandwidth.
  2. Four for each controller iirc
  3. Unsure

I would not describe it that way / call this unproven until somebody can show numbers for it.
Which leads me into

There is no fixed amount of PCIe lanes allocated, as it is all on the same die. You will also not find a PCIe-lane count for the iGPU, because it will not be using the lower/physical layers of PCIe, because that would just be wasteful. So far I have seen no documentation on the internal topology Intel uses to connect the USB controllers, chipset, external PCIe lanes directly from the CPU or the PCIe ports of the TB/USB4 ports.
All we know is, that it is at least the equivalent of x4 Gen 3, as you can reach the same throughput as on the older, external TB controllers that used one x4 Gen 3 connection for 2 ports (and the integrated USB3 controller).

We also know from documentation, that Intel is not using the same IP Cores as in the external controllers, as documentation and the PCI topology shows, that each TB port has its own PCIe Root Port (as the Microsoft spec for USB4 on Windows demands) and they share a single USB3 controller for all 4 ports. Gone are the explicitly visible PCIe bridges that the external controllers had, to share the single upstream PCIe connection for 2 TB-ports, the USB3 controller and the TB controller itself.

We do not know if those 4 root ports (that each can at least reach x4 Gen 3 speeds on their own) are attached to a dedicated crossbar that shares some amount of bandwidth across all ports or whether they simply share bandwidth with the other external PCIe ports (x8, x4, x4) from the CPU. (Theoretically it would be possible to have an entire hierarchy in between, not visible to us, where 2 PCIe root ports share some bandwidth, but why would that be the case).

We know from measurements with the new ASM2464 controllers, which support x4 Gen 4 output, that starting with 12th gen Intel, the integrated controllers can exceed the throughput of x4 Gen 3 PCIe connectivity, so the bandwidth shared across the TB ports will have at least increased proportionally.
But it would require tests with multiple external TB-NVMes to find out, just how much total bandwidth there is for all 4 TB ports.

Confirmed from Intel’s documentation is only, that the 2 DP connections are shared across 2 TB-ports (which are mapped to one side on the FW) and that the USB3 controller is shared across all 4.

That is nothing new. Previous platforms have already supported that. I can only say, that there is no such option for it in the 12th gen FW. And so far, I have only seen this in notebooks setup specifically for debugging windows. I have no idea whether that WinDbg functionality would be automatically equivalent to emulating any USB device from say, Linux / with the right drivers. It may more specific, I just don’t know.

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I guess I hadn’t considered that the moving of the TB controller on die removed vendor variability with the PCIe backend. Very good to know.

RE the xUDC, I am using it in Linux for all kids of USB gadget emulation, not for debugging in windows. I have been using some older laptops that have exposed the BIOS configuration for enabling the UDC, which works great, but they are aging. I was hoping that Frameworks openness to the community might present the opportunity to expose that configuration to the end-user since it is unlikely to cause any other issues on their end. Is this the correct place to request the configuration option from them?

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Oh, so it is actually universal device emulation, cool.
Yeah, the BIOS would have room to get a lot more enthusiast features. Question is, will they? As stated by Matt Hartley on another thread, they seem to not want to add features post launch with software, even though they do with HW upgrades and the software upgrades should be relatively portable at least over the 3 Intel generations.

Because there would be a ton of additional features that could be useful each to some limited portion of users and is sth. that is already present for Intel, which means it probably only needs to be enabled when building the BIOS and tested.

Stuff like ReBar support or the “disable BootROMs behind PCIe-Tunneling” option I want.

Or the keyboard backlight options with timeout and auto-brightness that might be even the same across all FW13 if they share pretty much identical SMCs and wiring.

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intresting thread we got here, sadly im unsure if we would be able to tho. havent seen the option in the stock firmware and coreboot isnt on any of the FW but teh chromebook version.
I learned about xDCI from this blogpost: 🤫 Unlocking secret ThinkPad functionality for emulating USB devices | Andrey Konovalov
and now after wondering about my FW, i sadly think Intel bootguard blocks us. unless FW devs might like to add such thing (experimentally maybe?)