Hello,
I cannot find specifics on the USB4 ports on the AMD Framework 13 Laptops. Yes, they support Display Port. The CPU supports 2x 40Gbps USB. Apparently some of you use eGPUs, so there should be some PCIe over USB support as well.
Do the USB4 ports support PCIe 3.0 x 4, or PCIe 4.0 x 4?
Does anybody know?
Thanks in advance.
Is there really much point to pcie 4 if the bandwidth is limited to less than full pcie3x4 anyway?
Currently no CPU supports PCIe 4.0 over USB4 as PCIe 4.0 support was a recent addition to the USB4 so. So it is limited to PCIe 3.0
Thanks for the info! I think they should add that info to their specs. It will only get more confusing in the future when CPUs do start to support it.
That is not really relevant in this context.
USB4 (as TB3 before) transfers PCIe packets encapsulated into USB4 packets. At this point they have no lanes or anything. The lower layers of the PCIe protocol that concern themselves with the connection speed and lanes are simply stripped away and only the more abstract PCIe packets are used by USB4/TB.
The notion of PCIe x4 Gen 3 for TB controllers comes from the external Intel TB controllers that were simply connected by a regular PCIe connection. Once these controllers are part of the CPU they might not even be attached via classic PCIe lanes. That could have all been simplified and they could just be limited to some total throughput of PCIe bandwidth as there does not need to be a generic PCIe connection between 2 parts of the same silicon die.
Intel’s device-side TB3 controllers so far have all been x4 Gen 3, so no matter what PCIe bandwidth the host has, the upper limit was that x4 Gen 3 bandwidth. Paired with USB4 overheads and the overhead of the subset of PCIe that previous TB/USB4 could tunnel you end up at the ~3.1 GiB/s of bandwidth that have been possible for a while with the Titan Ridge generation of TB3 controllers. Older Alpine Ridge controllers apparently had additional bottlenecks limiting them to ~2.6 GiB/s of actually usable bandwidth, below what PCIe x4 Gen 3 could have achieved.
But we know from reviews / measurements with the new ASM2464PD controllers or multiple TB/USB4 PCIe devices, that starting with 12th gen CPUs, Intel’s integrated USB4 controllers have access to at least enough PCIe bandwidth to saturate the entire 40G USB4 link (the 3.8 GiB/s often quoted for the ASM2464PD. This is also what you get when you apply all the known overheads for PCIe to the total 40G of USB4 bandwidths).
We have seen confirmation, of that bandwidth also being available on AMD’s USB4 implementation.
So far, I have seen nobody test the limits of that PCIe bandwidth (like 4 TB/USB4 NVMe drives on an FW13 12th gen or newer for total bandwidth measurements across all 4 ports simultaneously and maybe even including the native M.2 PCIe port), so we do not know how much more PCIe bandwidth than necessary to saturate one 40G USB4 link any of those implementations have.
PCIe x4 Gen 4 only comes into play again, when you need to convert the tunneled PCIe packets into a physical PCIe connection again in order to connect a regular PCIe device, like an M.2 NVMe SSD to the USB4 controller. But another manufacturer could be able to achieve exactly the same amount of PCIe bandwidth by using a x8 Gen 3 PCIe port. None of that should really matter to the USB4 host. It is even a question of whether you could trust say lspci or HWInfos reports on PCIe connections for sth. that is only virtual like what is transferred through a USB4 connection until it is reconstructed back into a real PCIe connection again.
And I still do not know whether it is even important for the PCIe protocol that the host accurately knows or can control which PCIe configuration is made between a PCIe bridge and attached devices. That information might also be entirely unreliable or irrelevant to it working.
I.e. when you see that a ASM2464PD controller shows up as having a x2 Gen 4 connection, does that actually mean that is what it has to the attached SSD? Or is that just what some software guesses based on the roughly available PCIe bandwidth or because PCIe drivers are expected to have this information, but it might be entirely fake.
Edit:
But you are right, no one right now is giving specific numbers for this. Intel is still the most specific, but all they’ll say is “3 GiB/s is the minimum guaranteed PCIe bandwidth across all USB4 ports”, which we know to be far from the maximum they can already achieve. It is just that the relevant numbers are in GiB/s (or GBit/s) not Lanes or such.
Thank you for the info! I did not know that it worked like that.