Feature Request: Extra Battery Expansion Bay WITH oculink 8i

With older controllers that is the case, however with newer controllers higher speeds can be achieved.

Thunderbolt doesn’t carry PCIe lanes, it carries PCIe data. When something says “4 PCIe 3.0 lanes” it means that is how the controller is treating it, however higher capabilities can be achieved.

The ASMedia ASM2464PD (a USB4v1 40 Gbps controller) can achieve 3.6 GiB/s (~31 Gbps) real world.

The Intel JHL9440 (a USB4v2 40 Gbps controller) can take advantage of lower overhead. Afaik there have not been any real world test results shared from that but I expect it to be around ~4 GiB/s (~34 Gbps) real world.

USB4v2 80 Gbps (aka Thunderbolt 5) should allow around double that at ~8 GiB/s (~69 Gbps) after overhead, although Intel’s initial controllers will probably be limited to ~6 GiB/s (~52 Gbps) due to limiting it to four PCIe 4.0 lanes.

Part of that is due to USB4v1 only allowing 128 byte payloads in PCIe tunneling. Each payload has a 22, 26, or 30 byte header. That means anywhere from 15-19% of the bandwidth is used just for headers.

Whereas with 256 byte payloads (which are supported by USB4v2 and Thunderbolt 5) only 8-10% of the bandwidth is used for headers.

That helps a bit.

A single PCIe 4.0 lane has a theoretical speed of 1.86 GiB/s before any overhead. In real world tests it comes in around 1.4 GiB/s (12 Gbps) after overhead.

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