Look at my PR in the github
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Such a shame, I was looking forward to a framework option! The GPDWinMax2 has this integrated, and we often see a 10% improvement over Thunderbolt.
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This sounds like an excellent idea. In the future, if I end up owning another Oculink-equipped device, this would make for a great way to re-use old GPU expansion bay modules.
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The framework team did mention a possible dual m.2 expansion bay. You may be able to add an oculink 8i card to one of those if the m.2 slot exposes pcie lanes.
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I like this thread. Relatively new here, it looks like nrp directly encouraging the community to develop something to then put in the FW Marketplace. What a great idea!
Oculink might be kinda niche, but this would be the place to try it for sure. It’ll be months before FW16 orders start being filled, I’m gonna sit back and watch… but if this expansion bay oculink adapter & dock becomes a thing, well, I might just change my own order for one!
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Thanks so much. Just started doing symbol&footprint myself when I saw this thread.
I just finished a very basic first implementation of an Oculink x4 port. I switched to KiCad for this job, first time using it. I’m not usually the one designing the PCBs but wanted to give it a try.
Routing PCI-E lanes is definitely not easy, had some trouble with impedance. Ended up using the JLC04121H-3313 stack from jlcpcb for controlled impedance, but KiCads internal calculator wanted thicker traces so I deviated a bit.
Also not entirely sure I got the pinout right, the RX lanes on the Motherboard (so the TX lanes on the daughterboard) are should be daughterboard->motherboard, so I connected them to the RX lines of the Oculink connector - correct?
CORRECTION much later: Input in the github interface pinout table means input to the daughterboard. So TX are actually motherboard → daughterboard. So TX interface pins should be connected to TX Oculink pins
Unfortunately a full-sized Oculink 8i faces a few difficulties, first the spec is not public, second even more high speed lanes will be difficult for me, an inexperienced router, to do.
One thing I do hope I can add in the future is a DP in port to switch output to the internal display. Will have to research what needs to be done so it does actually switch (or if a purely passive solution might work again).
Finally, I am not quite sure why the internal PCB outline has an uneven back edge, all photos from the shell imply the back can be fully used, but both the SSD and the base reference PCB on the github have a retreating edge. @nrp sorry for the ping but can you confirm the board can be expanded like this?
(Yes there’s still quite a bit to do before it is ready, right now the signal integrity is probably very bad.)
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Those that say OcuLink is niche are effectively saying that eGPU solutions are niche. TB4 eGPUs are inferior to OcuLink, OcuLink is the next step. FW should lead the charge, not these obscure brands that have a small market share.
It also fits in with their low-footprint and e-waste reduction philosophy.
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Thank you.
Where did you find josh cook’s github? i got an error 404 when i tried to find him.
And how did you do that now? Is there a turtorial for such things? How long did you need for that now? Do you think, with zero PCB-design-knowledge someone could be able to try the same (just for learning) in some hours? Or is that a thing of long learning process and knowledge of electrical stuff?
What do you mean by pinout? Where did you find the pinout for the 4i? maybe i can help searching.
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I just read an TI application note that recommends having the same amount of vias in a pair.
Thanks for working on this y’all! Seriously considering upgrading to the max-spec AMD board to replace my desktop, and Oculink would enable me to dock a “real” GPU. (I know TB3,4 is a thing, but reliability has always been sketch with Thunderbolt + Linux)
Exactly, oculink connection would allow many users to refrain from buying desktops. Many people have a desktop at home and an ultrabook for portability. While all you need is one notebook with oculink and an EGPU. This of course is all written in the name of sustainability ;):
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I’ve got a friend who develops PCB stuff for me usually. But that gave me a lot of the background needed. So I guess I knew what to look out for, but still very adept at implementing it. PCI-E is quite a tall order for a first PCB project, my implementation of it is still very crude and will need refinement. I watched a few videos on KiCAD workflow, PCI-E signalling, and controlled impedance for differential pairs. So yeah, there are good tutorials for each part, but you still need to know what to look for:) (Took me two days, but included an all-nighter)
As for specifications, that is a lot more approachable. PCI-SIG charges for the specs, but sometimes, you can get a hold of them in the mortal realm. You can see on their site that it’s named “PCI Express OCuLink Specification”. Physical footprint of the G14-series (the only ports actually available) are public luckily, as is the base connector known as SFF-8611 (SFF-8612 is the cable) - but neither describes the pinout. Sadly, the Oculink 8i pinout seems to be unreachable for now, need Revision 1.1 of said document for that, I can only find Revision 1.0 - or maybe my google skills are not sufficient.
Once you got the all the specs, you just put it into a symbol and then a footprint within KiCAD. This is time consuming but not too hard (and is valuable in itself, now a more experienced PCB designer has a lower barrier of entry to develop this). I’ll make sure to upload the OcuLink and modified Framework base files later
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I tried to find it, but i also don’t find that, only the rev. 1.0.
But ok, i mean probably we could just use 2 4x and use such a cable: https://de.aliexpress.com/item/1005005640106462.html?spm=a2g0o.productlist.main.39.f7f04f6evBve34&algo_pvid=2f953641-9863-4901-a8dc-3bb1c67746fd&aem_p4p_detail=202307311049513868936693559000017093022&algo_exp_id=2f953641-9863-4901-a8dc-3bb1c67746fd-19&pdp_npi=3%40dis!CHF!24.68!20.98!!!27.80!!%402101d8b516908257912101646eb941!12000033847646950!sea!CH!0&curPageLogUid=eIwIYMmVoeDF&search_p4p_id=202307311049513868936693559000017093022_12
Well worst case I can just disect any 8i product and reverse engineer it. As long as I know where 3V and 5V is as well as the PCI-E lanes, I should be good. Requires me to blindly buy multiple 50$+ products though when besides these basic but expensive OcuLink 8i to Full sized PCI-E adapters nothing uses 8i - all off-the-shelf eGPUs use x4 (though if you’re in it for the lower price you’d want a PSU+x16 adapter+desktop GPU anyway
Did you create the 4x footprint and symbol you’re using?
If so, it’s a bit late, but there is a 4x footprint and symbol here.
Yeah ok, that would probably to much expense.
But about the 8i and eGPU: i mean i would just buy a 8i to pci-e board and connect it there (with a 8i to 2x 4i adapter). They are available on aliexpress but yeah, if you want not to build it by yourself it will always be 4i, yes
You probably know this, but for others following, there are even 2x4i to 1x8i adapter cables…
Revision 1.0 of the datasheet has no pinout? Or do you think the pinout changed with rev 1.1?
There looks to be an 8i pinout in the listing for the cable Burt posted.
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I did, welp
But no matter
Heck yeah! Thanks, did not find it anywhere.
Rev 1.0 only includes x4, I think 8i (and the naming scheme change) was added later, presumably in Rev 1.1
But with that pinout we should be good!
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