The desktop seems to have 4 PCIe slots:
I am wondering which are directly connected to the CPU, which are connected via chipset, how many (electrical) lanes each one is. This is sometimes represented as a block diagram in motherboard manuals.
Does this help?
Modern (laptop) CPUs/Mainboards don’t really have chipsets anymore. I expect them to all go to the CPU and to have as many lanes as they would normally have (4 for NVMe, 1 for Wifi, 4 for PCIe).
The actual desktop ones certainly do (hell x670e has 2 of them in series XD) but this is true for laptop platforms which this is.
A lot of people use chipset and PCH interchangeably. Really I mean any form of IO controller that results in shared bandwidth to the CPU.
That link says there are 16 native and usable lanes of PCIe, which seems like enough for all IO to have dedicated lanes.
Still, I’d love to get a more definitive answer. It is extremely rare for consumer desktop motherboards to give directly-connected PCIe to the second M.2 slot, for example (probably because they usually have a lot more lanes allocated for actual PCIe slots).
This is a laptop CPU transplanted on a desktop mainboard. Also this is a community forum. if you want definitive answers, talk to Framework support or wait until they release official documentation.
I think this IS the right place to ask those questions as @Destroya moderates and there are other Framework team members participating. Additionally, we all benefit when these answers are shared
All from the CPU, as it has been with AMD mobile APUs for generations.
In fact, the total 16 lanes of Strix Point / Strix Halo is a downgrade from last generation, where AMD still had 20 PCIe lanes total
That is how the FW16 with Phoenix got to x8+x4+x4+x4 (the last one for WiFi and otherwise largely unused as it will be here) and why the current CPUs could not fully replace them.
Sorry for yet another link but I think these three images might be what you are after @Andrew_Hamon
for the last 4 It may have be use for:
for the desktop with “only” 16 line I can be:
)Use the MAX for the FW16 mean only 1 Nvme x4 and at best 1 Nvme x2 , 1 for the 6th USB3 … May be not that bad …
We’ll be sharing this on our github page in the future!
I have seen no documentation that AMD shares the physical pins between PCIe and USB3 on their CPUs. They have comparatively little ports to begin with, those are almost assuredly all dedicated.
FW16 Phoenix for example used a USB3 10G hub for the 2 ports closest to the front (plus one of the middle ports). Because the CPU only offered 2 native USB3 10G ports + the USB4 ports, which always include native USB3 themselves.
Yes, the Ethernet port on the Desktop will almost definitely by using PCIe as well.
With the back USB-A ports only being USB3 5G, they are most likely also dedicated, so that the front ports can be fed from the same native USB3 10G ports as on the notebooks, just without the DP connections muxed in, as they have dedicated outputs on the back… But that we’ll know when the schematics release.
Its actually sad, that sometimes the press decks will give info that the public specs won’t have, but also, they are also so wrong in technical terms that it also is of questionable reliability what AMD’s marketing people put together.
Does not use PCIe in the first place. Just USB2.
Actually, I was mainly thinking about having a USB controller on the PCIe lanes. But I should have looked at the published diagrams:
They actually (as you say.) added a USB hub to have two more ports rather than using part of the last three PCIe lanes with a suitable controller.
So maybe they did the same on the desktop and therefore two PCIe lanes aren’t used…