The product page mentions that the Framework Desktop supports USB4. What USB4 is this exactly? Speeds supported? PCIe? PCIe packet size? Power delivery? Networking? Thunderbolt 3? Which DisplayPort version and features? Anything else?
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Rear USB4 port DP Alt can display DP2.1 UHBR20 20Gb/s
We’ll try to update the specs more in the future 
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Good to know. But, yes, more specs please. Speed and packet sizes are kind of a big deal, as OP asked. Particularly for the cluster use-cases Framework mentioned on stage.
Edit: See also: USB4 - Wikipedia And I guess also good to know if we’re talking USB4 v2.0 or USB4 v1.0
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v2 doesn’t enforce anything new. Everything matching v1 is also valid v2.
Verbose lists of of optional usb4 features is the way to go.
- Speeds (Data and Display)
- Supported PD settings.
- …
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I got some answers!!
It is USB4 V1.
Supports PCIe and packet size is 128 Bytes.
Power delivery: 5V3A
Networking? Yes
Thunderbolt 3? Yes (we do not have specific thunderbolt certification for this product, thunderbolt 3 is supported as a legacy mode as part of the USB4 specification.)
DisplayPort version and features? HBR3.
Hope this helps!
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Thanks a lot! That seems to answer my most pressing questions
It seems that there is plenty of potential. A bit sad about the PCIe packet size, but that was expected.
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I’d like to come back to this question and seek further clarification, please. According to the AMD specs for the chip for this Framework Desktop, the Max+ 395 supports 2 x 40 Gbps USB 4 ports. I note in a reply that @Destroya said the ports were 20Gbps. I wonder if further information may have come to light? https://www.amd.com/en/products/processors/laptop/ryzen/ai-300-series/amd-ryzen-ai-max-plus-395.html
No. The only thing that was said with the number 20 in it was UHBR20. Which is a DP speed of 20 Gbit/s per wire-pair. This is more or less equivalent to USB4 Gen 3. And with DP you can combine all for wire-pairs for the total 80 Gbit/s DP connection.
But that is only for native output. Because the USB4 controllers from AMD are still only USB4v1, which did not include any of the new support for anything newer than DP 1.4 (for example speeds above HBR3), PCIe packet sizes larger than 128 Byte. Intel is doing it similarly and has also been supporting UHBR10 and UHBR20 DP speeds natively on their USB4 ports for a while, while still sticking to USB4v1.
This is the case, because DP more or less copied the work from USB4 for Gen 2 and Gen 3 (UHBR10, UHBR20). So its relatively easy to add those to existing USB4 40G ports. The weird part is, that only Strix Halo gets that UHBR20 support. Strix Point (FW13) is still limited to UHBR10.
Question here is: does Strix Halo also support UHBR13.5? Intel skips this entirely. But they are smart enough to at least list this explicitly. AMD is still very much unclear about that. UHBR13.5 does not match any existing USB4 speed. So that would be extra work.
TB3 support is basically mandated by Microsoft in order for it to qualify for Windows. So no CPU manufacturer that expects/hopes to run Windows would leave that out of USB4 host controllers until that changes. Same as with PCIe tunneling support, which is required for TB3 support.
And networking is basically purely software. You will always have that, if the controllers comply with the modern USB4 specifications, which Microsoft also requires. Meaning using the Windows 11 USB4 drivers. And previous AMD CPUs already could saturate the 40 Gbit/s connection with PCIe alone. So no reason to believe they throttled that now.
The one spec that was not mentioned is DP tunnel / input count for the USB4 controllers. But AMD has never specified those, making it seem like they had a subpar USB4 implementation, even though they have the same 2 DP inputs that Intel has and mandates with TB4.
And AMD so far used single-port USB4 controllers, such that each USB4 port has access to 2 separate DP inputs independently of each other. Where Intel uses dual-port controllers. Where 2 USB4 outputs are driven by the same USB4 controller that only has 2 DP inputs total available.
So far, AMD had also discrete USB3 10G controllers per USB4 controller (ensuring max. USB3 10G bandwidth per USB4 port), whereas Intel shared a single USB3 10G (20G in newer CPUs) across all 4 USB4 ports (with only a minimum shared bandwidth indicated, but unclear if it could saturate all 4 ports with USB3 simultaneously).
Yes it does. But its small. It requires support for larger PCIe packets (if PCIe tunneling is supported, which it will be for host controllers). So basically, all USB4v2 controllers will support 256 Byte packets. Which is pretty much the default for many things and brings the bandwidth efficiency of PCIe tunnels on par with native PCIe connections of many components. With v1 we are forced to loose a lot of PCIe bandwidth to the hard 128 Byte limit.
Edit:
I am led to believe AMD has supported 512 bytes for a while. I am unclear what USB4 says about that. The USB4 spec itself demands full support up to 4096 bytes. But Intel’s new controllers only explicitly mention 256 Bytes. And there might be a trick being played, where the PCIe switch (which can be a normal PCIe switch or could be deeply integrated) can limit to 256 Byte, even if the USB4 controller itself must be able to handle forwarding anything up to 4096 Bytes to that switch, not sure. For Intel it probably does not matter, because the Intel CPUs are still limited to 256 Byte anyway…
So details on end-to-end support might depend on the non-public USB-IF certification requirements…
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Thanks very much @Ray519 for the detailed technical response. TBH, I think understood some of what you said. Could you help by clarifying my ‘lay consumer’ interpretation as I’m trying to assess whether the Max+ 395 - 128GB Desktop will meet one of my use cases?
With two 4K (3840 x 2160) monitors connected via the two display ports (replaying a 1024 res video on each for example) on the FW Desktop, is it reasonable to expect the two USB 4 ports to simultainiously enable 40Gbps throughput (one read the other write) consistantly over an indeterminate period?
Thank you
While I tried to benchmark my 12th gen’s USB4 ports as much as I could given my available TB & USB4 devices, I have not done much testing with AMD’s USB4 ports.
But its almost irrelevant to look at USB4 as a whole. The 40G connection will remain stable.
But it consists of different tunnels. DP? Made for it, DP connections have no reason to fail, other than when there is interference. Which there is not on a virtual connection.
USB3? Not much different than bare USB3 connections. And with AMD, each USB4 port has its own PCIe-USB3 controller. So no problem at all. But also limited to 10 Gbit/s each, on the available information of AMD.
PCIe? This is where it gets interesting. Because in the end, all the PCIe ports of the system are basically merged together in a big interconnect and there is almost nothing tested or specced about what kind of throughput you could expect there in total. Typically, there should be nothing that decreases over time. PCIe bandwidth and memory bandwidth is just shared across many things.
Typically, we see CPU PCIe ports to have pretty much separate throughput (up to some arbitrary limit that barely anybody ever reaches).
You, just talking about a transfer from 1 USB4 port to the other? This should be just as fine, as transferring max. bandwidth from 1 SSD to another in an internal M.2 slot. Nobody actually measures this, we just assume that is fine. If a CPU would fail that, the manufacturer is likely to go under soon, because there is a lot they are doing wrong.
Monitor-wise: driving displays basically only consumes memory bandwidth proportionally. And we have lots of it with DDR5. 4x 4k60 is now a low-ball number for what iGPUs can handle there. That is like ~1.5 GB/s per monitor. Of like 60 GiB/s of memory bandwidth (for a normal SO-DIMM) system with modern DDR5. The Strix Halo CPU has A LOT more than that with its soldered memory optimized for GPU performance.
And we really have no tests to know that Intel’s implementation would be better. I can just tell you, that with eGPU and 2 TB NVMes, I can almost saturate 3 USB4 ports on my 12th gen without noticing any fall-off. And then I run out of devices to connect, not bandwidth. So PCIe bandwidth across different ports should be the least of your problems, as long as the total stays way under the available memory bandwidth in the system (as almost all transfers either go from or to memory).
Reliability of wholly uncertified USB4 port (neither TB4, nor USB4 (new Thinkpads and HP Notebooks have their AMD systems actually TB4 certified))? Now that can be questionable. But that is more about whether the device connects in the first place or survives sleeping…
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That’s very helpful, @Ray519 Thank you very much